With the development on the integrated circuit (IC) technology, the integration level of semiconductor devices has been continuously improved, which causes the number of conductive structures in a circuit to significantly increase; and the distances between the conductive structures to decrease. Thus, a resistive capacitive delay (RC delay) effect caused by parasitic capacitances and parasitic resistances becomes more severe. In order to reduce the RC delay effect caused by the parasitic capacitances and the parasitic resistances, low dielectric constant (low-K) materials are used to isolate the conductive structures. The low-K material reduces the parasitic capacitances between the conductive structures, thus the RC delay effect caused by the parasitic capacitances and parasitic resistances is reduced.
FIGS. 1˜4 illustrate semiconductor structures corresponding to certain stages of an exemplary process for forming a conductive structure with a low-K dielectric layer.
As shown in FIG. 1, the process includes providing a semiconductor substrate 100 having semiconductor devices (not shown) formed inside; and forming a low-K dielectric layer 101 on one surface of the semiconductor substrate 100.
Further, as shown in FIG. 2, the process also includes forming a buffer layer 102 on the top surface of the low-K dielectric layer 101; forming a hard mask layer 103 on the top surface of the buffer layer 102; forming a titanium nitride (TiN) layer 104 on the top surface of the hard mask layer 103; and forming a patterned photoresist layer 105 on the top surface of the TiN layer 104. The buffer layer 102 is made of silicon oxynitride (SiON); and may be referred a hard mask buffer layer (HMBD). The hard mask layer 103 is made of tetraethyl orthosilicate (TEOS); and may refer to a HDTEOS layer
Further, as shown in FIG. 3, the process includes etching the TiN layer 104, the hard mask layer 103 and the buffer layer 102 until the surface of the low-K dielectric layer 101 is exposed using the patterned photoresist layer 105 as an etching mask; and etching the low-K dielectric layer 101 until the surface of the semiconductor substrate 100 is exposed using the etched TiN layer 104, the etched hard mask layer 103 and the etched buffer layer 102 as an etching mask; and an opening 106 is formed in the low-K dielectric layer 101. After forming the opening 106, the photoresist layer 105 may be removed.
Further, as shown in FIG. 4, the process also includes performing a wet chemical cleaning process; and forming a conductive structure 107 in the opening 106. Specifically, a process for forming the conductive structure 107 includes forming a conductive thin film on the surface of the TiN layer 104 and filling up the opening 106 with conductive material; and polishing the conductive film until the surface of the hard mask layer 103 is exposed. Thus, the conductive structure 107 is formed.
However, sidewalls of the opening 106 often have substantial undercuts after the etching processes for forming the opening 106. After forming the conductive structure 107, voids may be formed between the conductive structure 107 and the sidewalls of the opening 106, i.e., an overhang structure. It may also be easy to form voids in the conductive structure 107. Thus, the performance of the conductive structure 107 may be unstable. The disclosed device structures and methods are directed to solve one or more problems set forth above and other problems.